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1/34 february 2002 m95160 m95080 16/8 kbit serial spi bus eeprom with high speed clock features summary n compatible with spi bus serial interface (positive clock spi modes) n single supply voltage: 4.5v to 5.5v for m95xxx 2.5v to 5.5v for m95xxx-w 1.8v to 3.6v for m95xxx-s n high speed 5 mhz clock rate (maximum) with 10 ms write time (maximum) 10 mhz clock rate with 5 ms write time (product under development) n status register n hardware protection of the status register n byte and page write (up to 32 bytes) n self-timed programming cycle n adjustable size read-only eeprom area n enhanced esd protection n more than 1,000,000 erase/write cycles n more than 40 year data retention figure 1. packages pdip8 (bn) 0.25 mm frame 8 1 so8 (mn) 150 mil width 8 1 tssop8 (dw) 169 mil width tssop14 (dl) 169 mil width
m95160, m95080 2/34 summary description these electrically erasable programmable memo- ry (eeprom) devices are accessed by a high speed spi-compatible bus. the memory array is organised as 2048 x 8 bit (m95160), and 1024 x 8 bit (m95080). the device is accessed by a simple serial interface that is spi-compatible. the bus signals are c, d and q, as shown in table 1 and figure 2. the device is selected when chip select (s) is tak- en low. communications with the device can be interrupted using hold (hold). figure 2. logic diagram figure 3. dip connections figure 4. so8 and tssop8 connections figure 5. tssop14 connections note: 1. nc = not connected table 1. signal names ai01789c s v cc m95xxx hold v ss w q c d d v ss c hold q sv cc w ai01790c m95xxx 1 2 3 4 8 7 6 5 c serial clock d serial data input q serial data output s chip select w write protect hold hold v cc supply voltage v ss ground 1 ai01791c 2 3 4 8 7 6 5d v ss c hold q sv cc w m95xxx 1 ai02346b 2 3 4 14 9 10 8d v ss wc s hold m95xxx nc q nc nc nc nc nc 5 6 7 12 13 11 v cc
3/34 m95160, m95080 signal description during all operations, v cc must be held stable and within the specified valid range: v cc (min) to v cc (max). all of the input and output signals must be held high or low (according to voltages of v ih ,v oh ,v il or v ol , as specified in tables 13 to 17). these sig- nals are described next. serial data output (q). this output signal is used to transfer data serially out of the device. data is shifted out on the falling edge of serial clock (c). serial data input (d). this input signal is used to transfer data serially into the device. it receives in- structions, addresses, and the data to be written. values are latched on the rising edge of serial clock (c). serial clock (c). this input signal provides the timing of the serial interface. instructions, address- es, or data present at serial data input (d) are latched on the rising edge of serial clock (c). data on serial data output (q) changes after the falling edge of serial clock (c). chip select (s). when this input signal is high, the device is deselected and serial data output (q) is at high impedance. unless an internal write cycle is in progress, the device will be in the stand- by mode. driving chip select (s) low enables the device, placing it in the active power mode. after power-up, a falling edge on chip select (s) is required prior to the start of any instruction. hold (hold). the hold (hold) signal is used to pause any serial communications with the device without deselecting the device. during the hold condition, the serial data output (q) is high impedance, and serial data input (d) and serial clock (c) are don't care. to start the hold condition, the device must be se- lected, with chip select (s) driven low. write protect (w). the main purpose of this in- put signal is to freeze the size of the area of mem- ory that is protected against write instructions (as specified by the values in the bp1 and bp0 bits of the status register). this pin must be driven either high or low, and must be stable during all write operations. connecting to the spi bus these devices are fully compatible with the spi protocol. all instructions, addresses and input data bytes are shifted in to the device, most significant bit first. the serial data input (d) is sampled on the first rising edge of the serial clock (c) after chip select (s) goes low. all output data bytes are shifted out of the device, most significant bit first. the serial data output (q) is latched on the first falling edge of the serial clock (c) after the instruction (such as the read from memory array and read status register instructions) have been clocked into the device. figure 6 shows three devices, connected to an mcu, on a spi bus. only one device is selected at a time, so only one device drives the serial data output (q) line at a time, all the others being high impedance.
m95160, m95080 4/34 figure 6. bus master and memory devices on the spi bus note: 1. the write protect (w) and hold (hold) signals should be driven, high or low as appropriate. spi modes these devices can be driven by a microcontroller with its spi peripheral running in either of the two following modes: cpol=0, cpha=0 cpol=1, cpha=1 for these two modes, input data is latched in on the rising edge of serial clock (c), and output data is available from the falling edge of serial clock (c). the difference between the two modes, as shown in figure 7, is the clock polarity when the bus master is in stand-by mode and not transferring data: c remains at 0 for (cpol=0, cpha=0) c remains at 1 for (cpol=1, cpha=1) figure 7. spi modes supported ai03746d bus master (st6, st7, st9, st10, others) spi memory device sdo sdi sck cqd s spi memory device cqd s spi memory device cqd s cs3 cs2 cs1 spi interface with (cpol, cpha) = (0, 0) or (1, 1) w hold w hold w hold ai01438b c msb cpha d 0 1 cpol 0 1 q c msb
5/34 m95160, m95080 operating features power-up when the power supply is turned on, v cc rises from v ss to v cc . during this time, the chip select (s) must be al- lowed to follow the v cc voltage. it must not be al- lowed to float, but should be connected to v cc via a suitable pull-up resistor. as a built in safety feature, chip select (s) is edge sensitive as well as level sensitive. after power- up, the device does not become selected until a falling edge has first been detected on chip select (s). this ensures that chip select (s) must have been high, prior to going low to start the first op- eration. power on reset: v cc lock-out write protect in order to prevent data corruption and inadvertent write operations during power-up, a power on reset (por) circuit is included. the internal reset is held active until v cc has reached the por threshold value, and all operations are disabled the device will not respond to any command. in the same way, when v cc drops from the operating voltage, below the por threshold value, all oper- ations are disabled and the device will not respond to any command. a stable and valid v cc must be applied before ap- plying any logic signal. power-down at power-down, the device must be deselected. chip select (s) should be allowed to follow the voltage applied on v cc . active power and stand-by power modes when chip select (s) is low, the device is en- abled, and in the active power mode. the device consumes i cc , as specified in tables 13 to 17. when chip select (s) is high, the device is dis- abled. if an erase/write cycle is not currently in progress, the device then goes in to the stand-by power mode, and the device consumption drops to i cc1 . hold condition the hold (hold) signal is used to pause any se- rial communications with the device without reset- ting the clocking sequence. during the hold condition, the serial data output (q) is high impedance, and serial data input (d) and serial clock (c) are don't care. to enter the hold condition, the device must be selected, with chip select (s) low. normally, the device is kept selected, for the whole duration of the hold condition. deselecting the de- vice while it is in the hold condition, has the effect of resetting the state of the device, and this mech- anism can be used if it is required to reset any pro- cesses that had been in progress. the hold condition starts when the hold (hold) signal is driven low at the same time as serial clock (c) already being low. the hold condition ends when the hold (hold) signal is driven high at the same time as serial clock (c) already being low. status register figure 8 shows the position of the status register in the control logic of the device. the status reg- ister contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. wip bit. the write in progress (wip) bit indicates whether the memory is busy with a write or write status register cycle. wel bit. the write enable latch (wel) bit indi- cates the status of the internal write enable latch. bp1, bp0 bits. the block protect (bp1, bp0) bits are non-volatile. they define the size of the area to be software protected against write instructions. srwd bit. the status register write disable (srwd) bit is operated in conjunction with the write protect (w) signal. the status register write disable (srwd) bit and write protect (w) signal allow the device to be put in the hardware protected mode. in this mode, the non-volatile bits of the status register (srwd, bp1, bp0) become read-only bits. table 2. status register format b7 b0 srwd 0 0 0 bp1 bp0 wel wip status register write protect block protect bits write enable latch bit write in progress bit
m95160, m95080 6/34 data protection and protocol control non-volatile memory devices can be used in envi- ronments that are particularly noisy, and within ap- plications that could experience problems if memory bytes are corrupted. consequently, the device features the following data protection mechanisms: n write and write status register instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution. n all instructions that modify data must be preceded by a write enable (wren) instruction to set the write enable latch (wel) bit . this bit is returned to its reset state by the following events: power-up write disable (wrdi) instruction completion write status register (wrsr) instruction completion write (write) instruction completion n the block protect (bp1, bp0) bits allow part of the memory to be configured as read-only. this is the software protected mode (spm). n the write protect (w) signal allows the block protect (bp1, bp0) bits to be protected. this is the hardware protected mode (hpm). for any instruction to be accepted, and executed, chip select (s) must be driven high after the rising edge of serial clock (c) for the last bit of the in- struction, and before the next rising edge of serial clock (c). two points need to be noted in the previous sen- tence: the `last bit of the instruction' can be the eighth bit of the instruction code, or the eighth bit of a data byte, depending on the instruction (except for read status register (rdsr) and read (read) instructions). the `next rising edge of serial clock (c)' might (or might not) be the next bus transaction for some other device on the spi bus. table 3. write-protected block size status register bits protected block array addresses protected bp1 bp0 m95160 m95080 0 0 none none none 0 1 upper quarter 0600h - 07ffh 0300h - 03ffh 1 0 upper half 0400h - 07ffh 0200h - 03ffh 1 1 whole memory 0000h - 07ffh 0000h - 03ffh
7/34 m95160, m95080 memory organization the memory is organized as shown in figure 8. figure 8. block diagram ai01272c hold s w control logic high voltage generator i/o shift register address register and counter data register 1 page x decoder y decoder c d q size of the read only eeprom area status register
m95160, m95080 8/34 instructions each instruction starts with a single-byte code, as summarized in table 4. if an invalid instruction is sent (one not contained in table 4), the device automatically deselects it- self. table 4. instruction set figure 9. write enable (wren) sequence write enable (wren) the write enable latch (wel) bit must be set prior to each write and wrsr instruction. the only way to do this is to send a write enable instruction to the device. as shown in figure 9, to send this instruction to the device, chip select (s) is driven low, and the bits of the instruction byte are shifted in, on serial data input (d). the device then enters a wait state. it waits for a the device to be deselected, by chip select (s) being driven high. instruc tion description instruction format wren write enable 0000 0110 wrdi write disable 0000 0100 rdsr read status register 0000 0101 wrsr write status register 0000 0001 read read from memory array 0000 0011 write write to memory array 0000 0010 c d ai02281e s q 2 1 34567 high impedance 0 instruction
9/34 m95160, m95080 figure 10. write disable (wrdi) sequence write disable (wrdi) one way of resetting the write enable latch (wel) bit is to send a write disable instruction to the device. as shown in figure 10, to send this instruction to the device, chip select (s) is driven low, and the bits of the instruction byte are shifted in, on serial data input (d). the device then enters a wait state. it waits for a the device to be deselected, by chip select (s) be- ing driven high. the write enable latch (wel) bit, in fact, be- comes reset by any of the following events: power-up wrdi instruction execution wrsr instruction completion write instruction completion. c d ai03750d s q 2 1 34567 high impedance 0 instruction
m95160, m95080 10/34 figure 11. read status register (rdsr) sequence read status register (rdsr) the read status register (rdsr) instruction allows the status register to be read. the status register may be read at any time, even while a write or write status register cycle is in progress. when one of these cycles is in progress, it is recommended to check the write in progress (wip) bit before sending a new instruction to the device. it is also possible to read the status register continuously, as shown in figure 11. the status and control bits of the status register are as follows: wip bit. the write in progress (wip) bit indicates whether the memory is busy with a write or write status register cycle. when set to 1, such a cycle is in progress, when reset to 0 no such cycle is in progress. wel bit. the write enable latch (wel) bit indi- cates the status of the internal write enable latch. when set to 1 the internal write enable latch is set, when set to 0 the internal write enable latch is reset and no write or write status register in- struction is accepted. bp1, bp0 bits. the block protect (bp1, bp0) bits are non-volatile. they define the size of the area to be software protected against write instructions. these bits are written with the write status regis- ter (wrsr) instruction. when one or both of the block protect (bp1, bp0) bits is set to 1, the rele- vant memory area (as defined in table 2) be- comes protected against write (write) instructions. the block protect (bp1, bp0) bits can be written provided that the hardware protect- ed mode has not been set. srwd bit. the status register write disable (srwd) bit is operated in conjunction with the write protect (w) signal. the status register write disable (srwd) bit and write protect (w) signal allow the device to be put in the hardware protected mode (when the status register write disable (srwd) bit is set to 1, and write protect (w) is driven low). in this mode, the non-volatile bits of the status register (srwd, bp1, bp0) become read-only bits and the write status register (wrsr) instruction is no longer accepted for execution. c d s 2 1 3 4 5 6 7 8 9 10 11 12 13 14 15 instruction 0 ai02031e q 76543210 status register out high impedance msb 76543210 status register out msb 7
11/34 m95160, m95080 figure 12. write status register (wrsr) sequence write status register (wrsr) the write status register (wrsr) instruction al- lows new values to be written to the status regis- ter. before it can be accepted, a write enable (wren) instruction must previously have been ex- ecuted. after the write enable (wren) instruction has been decoded and executed, the device sets the write enable latch (wel). the write status register (wrsr) instruction is entered by driving chip select (s) low, followed by the instruction code and the data byte on serial data input (d). the instruction sequence is shown in figure 12. the write status register (wrsr) instruction has no effect on b6, b5, b4, b1 and b0 of the status register. b6, b5 and b4 are always read as 0. chip select (s) must be driven high after the rising edge of serial clock (c) that latches in the eighth bit of the data byte, and before the next rising edge of serial clock (c). otherwise, the write status register (wrsr) instruction is not executed. as soon as chip select (s) is driven high, the self- timed write status register cycle (whose duration is t w ) is initiated. while the write status register cycle is in progress, the status register may still be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 dur- ing the self-timed write status register cycle, and is 0 when it is completed. when the cycle is com- pleted, the write enable latch (wel) is reset. the write status register (wrsr) instruction al- lows the user to change the values of the block protect (bp1, bp0) bits, to define the size of the area that is to be treated as read-only, as defined in table 2. the write status register (wrsr) instruction also allows the user to set or reset the status register write disable (srwd) bit in accordance with the write protect (w) signal. the status register write disable (srwd) bit and write protect (w) signal allow the device to be put in the hardware protected mode (hpm). the write status register (wrsr) instruction is not executed once the hard- ware protected mode (hpm) is entered. the contents of the status register write disable (srwd) and block protect (bp1, bp0) bits are fro- zen at their current values from just before the start of the execution of write status register (wrsr) instruction. the new, updated, values take effect at the moment of completion of the ex- ecution of write status register (wrsr) instruc- tion. c d ai02282d s q 2 1 3 4 5 6 7 8 9 10 11 12 13 14 15 high impedance instruction status register in 0 765432 0 1 msb
m95160, m95080 12/34 table 5. protection modes note: 1. as defined by the values in the block protect (bp1, bp0) bits of the status register, as shown in table 5. the protection features of the device are summa- rized in table 3. when the status register write disable (srwd) bit of the status register is 0 (its initial delivery state), it is possible to write to the status register provided that the write enable latch (wel) bit has previously been set by a write enable (wren) in- struction, regardless of the whether write protect (w) is driven high or low. when the status register write disable (srwd) bit of the status register is set to 1, two cases need to be considered, depending on the state of write protect (w): if write protect (w) is driven high, it is possible to write to the status register provided that the write enable latch (wel) bit has previously been set by a write enable (wren) instruction. if write protect (w) is driven low, it is not pos- sible to write to the status register even if the write enable latch (wel) bit has previously been set by a write enable (wren) instruction. (attempts to write to the status register are re- jected, and are not accepted for execution). as a consequence, all the data bytes in the memo- ry area that are software protected (spm) by the block protect (bp1, bp0) bits of the status reg- ister, are also hardware protected against data modification. regardless of the order of the two events, the hardware protected mode (hpm) can be entered: by setting the status register write disable (srwd) bit after driving write protect (w) low or by driving write protect (w) low after setting the status register write disable (srwd) bit. the only way to exit the hardware protected mode (hpm) once entered is to pull write protect (w) high. if write protect (w) is permanently tied high, the hardware protected mode (hpm) can never be activated, and only the software protected mode (spm), using the block protect (bp1, bp0) bits of the status register, can be used. table 6. address range bits note: 1. b15 to b11 are don't care on the m95160. b15 to b10 are don't care on the m95080. w signal srwd bit mode write protection of the status register memory content protected area 1 unprotected area 1 10 software protected (spm) status register is writable (if the wren instruction has set the wel bit) the values in the bp1 and bp0 bits can be changed write protected ready to accept write instructions 00 11 01 hardware protected (hpm) status register is hardware write protected the values in the bp1 and bp0 bits cannot be changed write protected ready to accept write instructions device m95160 m95080 address bits a10-a0 a9-a0
13/34 m95160, m95080 figure 13. read from memory array (read) sequence note: depending on the memory size, as shown in table 6, the most significant address bits are don't care. read from memory array (read) as shown in figure 13, to send this instruction to the device, chip select (s) is first driven low. the bits of the instruction byte and address bytes are then shifted in, on serial data input (d). the ad- dress is loaded into an internal address register, and the byte of data at that address is shifted out, on serial data output (q). if chip select (s) continues to be driven low, the internal address register is automatically incre- mented, and the byte of data at the new address is shifted out. when the highest address is reached, the address counter rolls over to zero, allowing the read cycle to be continued indefinitely. the whole memory can, therefore, be read with a single read instruc- tion. the read cycle is terminated by driving chip se- lect (s) high. the rising edge of the chip select (s) signal can occur at any time during the cycle. the first byte addressed can be any byte within any page. the instruction is not accepted, and is not execut- ed, if a write cycle is currently in progress. c d ai01793d s q 15 2 1 3 4 5 6 7 8 9 10 2021222324252627 14 13 3 2 1 0 28 29 30 76543 1 7 0 high impedance data out 1 instruction 16-bit address 0 msb msb 2 31 data out 2
m95160, m95080 14/34 figure 14. byte write (write) sequence note: depending on the memory size, as shown in table 6, the most significant address bits are don't care. write to memory array (write) as shown in figure 14, to send this instruction to the device, chip select (s) is first driven low. the bits of the instruction byte, address byte, and at least one data byte are then shifted in, on serial data input (d). the instruction is terminated by driving chip se- lect (s) high at a byte boundary of the input data. in the case of figure 14, this occurs after the eighth bit of the data byte has been latched in, in- dicating that the instruction is being used to write a single byte. the self-timed write cycle starts, and continues for a period t wc (as specified in ta- bles 18 to 22), at the end of which the write in progress (wip) bit is reset to 0. if, though, chip select (s) continues to be driven low, as shown in figure 15, the next byte of input data is shifted in, so that more than a single byte, starting from the given address towards the end of the same page, can be written in a single internal write cycle. each time a new data byte is shifted in, the least significant bits of the internal address counter are incremented. if the number of data bytes sent to the device exceeds the page boundary, the inter- nal address counter rolls over to the beginning of the page, and the previous data there are overwrit- ten with the incoming data. (the page size of these devices is 32 bytes). the instruction is not accepted, and is not execut- ed, under the following conditions: if the write enable latch (wel) bit has not been set to 1 (by executing a write enable instruction just before) if a write cycle is already in progress if the device has not been deselected, by chip select (s) being driven high, at a byte boundary (after the eighth bit, b0, of the last data byte that has been latched in) if the addressed page is in the region protected by the block protect (bp1 and bp0) bits. c d ai01795d s q 15 2 1 3 4 5 6 7 8 9 10 2021222324252627 14 13 3 2 1 0 28 29 30 high impedance instruction 16-bit address 0 765432 0 1 data byte 31
15/34 m95160, m95080 figure 15. page write (write) sequence note: depending on the memory size, as shown in table 6, the most significant address bits are don't care. c d ai01796d s 34 33 35 36 37 38 39 40 41 42 44 45 46 47 32 c d s 15 2 1 3 4 5 6 7 8 9 10 2021222324252627 14 13 3 2 1 0 28 29 30 instruction 16-bit address 0 765432 0 1 data byte 1 31 43 765432 0 1 data byte 2 765432 0 1 data byte 3 65432 0 1 data byte n
m95160, m95080 16/34 power-up and delivery state power-up state after power-up, the device is in the following state: stand-by mode deselected (after power-up, a falling edge is re- quired on chip select (s) before any instruc- tions can be started). not in the hold condition the write enable latch (wel) is reset to 0 write in progress (wip) is reset to 0 the srwd, bp1 and bp0 bits of the status regis- ter are unchanged from the previous power-down (they are non-volatile bits). initial delivery state the device is delivered with the memory array set at all 1s (ffh). the status register write disable (srwd) and block protect (bp1 and bp0) bits are initialized to 0.
17/34 m95160, m95080 maximum rating stressing the device above the rating listed in the absolute maximum ratingso table may cause per- manent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not im- plied. exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality docu- ments. table 7. absolute maximum ratings note: 1. ipc/jedec j-std-020a 2. jedec std jesd22-a114a (c1=100 pf, r1=1500 w , r2=500 w ) symbol parameter min. max. unit t stg storage temperature 65 150 c t lead lead temperature during soldering pdip: 10 seconds so: 20 seconds (max) 1 tssop: 20 seconds (max) 1 260 235 235 c v o output voltage 0.3 v cc +0.6 v v i input voltage 0.3 6.5 v v cc supply voltage 0.3 6.5 v v esd electrostatic discharge voltage (human body model) 2 4000 4000 v
m95160, m95080 18/34 dc and ac parameters this section summarizes the operating and mea- surement conditions, and the dc and ac charac- teristics of the device. the parameters in the dc and ac characteristic tables that follow are de- rived from tests performed under the measure- ment conditions summarized in the relevant tables. designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parame- ters. table 8. operating conditions (m95xxx) table 9. operating conditions (m95xxx-w) table 10. operating conditions (m95xxx-s) note: 1. this product is under development. for more information, please contact your nearest st sales office. table 11. ac measurement conditions note: 1. output hi-z is defined as the point where data out is no longer driven. figure 16. ac measurement i/o waveform symbol parameter min. max. unit v cc supply voltage 4.5 5.5 v t a ambient operating temperature (range 6) 40 85 c ambient operating temperature (range 3) 40 125 c symbol parameter min. max. unit v cc supply voltage 2.5 5.5 v t a ambient operating temperature (range 6) 40 85 c ambient operating temperature (range 3) 40 125 c symbol parameter 1 min. max. unit v cc supply voltage 1.8 3.6 v t a ambient operating temperature 40 85 c symbol parameter min. max. unit c l load capacitance 100 pf input rise and fall times 50 ns input pulse voltages 0.2v cc to 0.8v cc v input and output timing reference voltages 0.3v cc to 0.7v cc v ai00825 0.8v cc 0.2v cc 0.7v cc 0.3v cc
19/34 m95160, m95080 table 12. capacitance note: sampled only, not 100% tested, at t a =25 c and a frequency of 5 mhz. table 13. dc characteristics (m95xxx, temperature range 6) note: 1. for all 5v range devices, the device meets the output requirements for both ttl and cmos standards. 2. preliminary: this product is under development. for more information, please contact your nearest st sales office. table 14. dc characteristics (m95xxx, temperature range 3) note: 1. for all 5v range devices, the device meets the output requirements for both ttl and cmos standards. 2. preliminary: this product is under development. for more information, please contact your nearest st sales office. symbol parameter test condition min . max . unit c out output capacitance (q) v out =0v 8 pf c in input capacitance (d) v in =0v 8 pf input capacitance (other pins) v in =0v 6 pf symbol parameter test condition min. max. min. 2 max. 2 unit i li input leakage current v in =v ss or v cc 2 2 m a i lo output leakage current s = v cc ,v out =v ss or v cc 2 2 m a i cc supply current c = 0.1 v cc /0.9. v cc at 5 mhz, v cc = 5 v, q = open 45ma i cc1 supply current (stand-by) s=v cc ,v cc =5v v in =v ss or v cc 10 2 m a v il input low voltage 0.3 0.3 v cc 0.3 0.3 v cc v v ih input high voltage 0.7 v cc v cc +1 0.7 v cc v cc +1 v v ol 1 output low voltage i ol = 2 ma, v cc =5v 0.4 0.4 v v oh 1 output high voltage i oh =2ma,v cc = 5 v 0.8 v cc 0.8 v cc v symbol parameter test condition min. max. min. 2 max. 2 unit i li input leakage current v in =v ss or v cc 2 2 m a i lo output leakage current s=v cc ,v out =v ss or v cc 2 2 m a i cc supply current c = 0.1 v cc /0.9. v cc at 2 mhz, v cc = 5 v, q = open 42ma i cc1 supply current (stand-by) s=v cc ,v cc =5v v in =v ss or v cc 10 5 m a v il input low voltage 0.3 0.3 v cc 0.3 0.3 v cc v v ih input high voltage 0.7 v cc v cc +1 0.7 v cc v cc +1 v v ol 1 output low voltage i ol = 2 ma, v cc = 5 v 0.4 0.4 v v oh 1 output high voltage i oh =2ma,v cc = 5 v 0.8 v cc 0.8 v cc v
m95160, m95080 20/34 table 15. dc characteristics (m95xxx-w, temperature range 6) note: 1. preliminary: this product is under development. for more information, please contact your nearest st sales office. table 16. dc characteristics (m95xxx-w, temperature range 3) note: 1. preliminary: this product is under development. for more information, please contact your nearest st sales office. table 17. dc characteristics (m95xxx-s) note: 1. preliminary: this product is under development. for more information, please contact your nearest st sales office. symbol parameter test condition min. max. min. 1 max. 1 unit i li input leakage current v in =v ss or v cc 2 2 m a i lo output leakage current s=v cc ,v out =v ss or v cc 2 2 m a i cc supply current c = 0.1 v cc /0.9. v cc at 2 mhz, v cc = 2.5 v, q = open 21ma i cc1 supply current (stand-by) s=v cc ,v cc =2.5v v in =v ss or v cc 20.5 m a v il input low voltage 0.3 0.3 v cc 0.3 0.3 v cc v v ih input high voltage 0.7 v cc v cc +1 0.7 v cc v cc +1 v v ol output low voltage i ol = 1.5 ma, v cc = 2.5 v 0.4 0.4 v v oh output high voltage i oh = 0.4 ma, v cc = 2.5 v 0.8 v cc 0.8 v cc v symbol parameter test condition min. max. min. 1 max. 1 unit i li input leakage current v in =v ss or v cc 2 2 m a i lo output leakage current s = v cc ,v out =v ss or v cc 2 2 m a i cc supply current c = 0.1 v cc /0.9. v cc at 2 mhz, v cc = 2.5 v, q = open 51ma i cc1 supply current (stand-by) s=v cc ,v cc =2.5v v in =v ss or v cc 22 m a v il input low voltage 0.3 0.3 v cc 0.3 0.3 v cc v v ih input high voltage 0.7 v cc v cc +1 0.7 v cc v cc +1 v v ol output low voltage i ol = 1.5 ma, v cc = 2.5 v 0.4 0.4 v v oh output high voltage i oh = 0.4 ma, v cc = 2.5 v 0.8 v cc 0.8 v cc v symbol parameter test condition min. 1 max. 1 unit i li input leakage current v in =v ss or v cc 2 m a i lo output leakage current s=v cc ,v out =v ss or v cc 2 m a i cc supply current c = 0.1 v cc /0.9. v cc at 1 mhz, v cc = 1.8 v, q = open 1ma i cc1 supply current (stand-by) s = v cc ,v in =v ss or v cc ,v cc = 1.8 v 0.3 m a v il input low voltage 0.3 0.3 v cc v v ih input high voltage 0.7 v cc v cc +1 v v ol output low voltage i ol = 0.15 ma, v cc = 1.8 v 0.3 v v oh output high voltage i oh = 0.1 ma, v cc = 1.8 v 0.8 v cc v
21/34 m95160, m95080 table 18. ac characteristics (m95xxx, temperature range 6) note: 1. t ch +t cl 1/f c . 2. value guaranteed by characterization, not 100% tested in production. 3. to be characterized. 4. preliminary: this product is under development. for more information, please contact your nearest st sales office. test conditions specified in table 11 and table 8 symbol alt. parameter min. max. min. 4 max. 4 unit f c f sck clock frequency d.c. 5 d.c. 10 mhz t slch t css1 s active setup time 90 15 ns t shch t css2 s not active setup time 90 15 ns t shsl t cs s deselect time 100 40 ns t chsh t csh s active hold time 90 25 ns t chsl s not active hold time 90 15 ns t ch 1 t clh clock high time 90 40 ns t cl 1 t cll clock low time 90 40 ns t clch 2 t rc clock rise time 1 1 m s t chcl 2 t fc clock fall time 1 1 m s t dvch t dsu data in setup time 20 15 ns t chdx t dh data in hold time 30 15 ns t hhch clock low hold time after hold not active 70 15 ns t hlch clock low hold time after hold active 40 20 ns t clhl clock high set-up time before hold active 0 0 ns t clhh clock high set-up time before hold not active 0 0 ns t shqz 2 t dis output disable time 100 25 ns t clqv t v clock low to output valid 60 25 ns t clqx t ho output hold time 0 0 ns t qlqh 2 t ro output rise time 50 20 ns t qhql 2 t fo output fall time 50 20 ns t hhqx 2 t lz hold high to output low-z 50 25 ns t hlqz 2 t hz hold low to output high-z 100 25 ns t w t wc write time 10 5 ms
m95160, m95080 22/34 table 19. ac characteristics (m95xxx, temperature range 3) note: 1. t ch +t cl 1/f c . 2. value guaranteed by characterization, not 100% tested in production. 3. to be characterized. 4. preliminary: this product is under development. for more information, please contact your nearest st sales office. test conditions specified in table 11 and table 8 symbol alt. parameter min. max. min. 4 max. 4 unit f c f sck clock frequency d.c. 2 d.c. 5 mhz t slch t css1 s active setup time 200 90 ns t shch t css2 s not active setup time 200 90 ns t shsl t cs s deselect time 200 100 ns t chsh t csh s active hold time 200 90 ns t chsl s not active hold time 200 90 ns t ch 1 t clh clock high time 200 90 ns t cl 1 t cll clock low time 200 90 ns t clch 2 t rc clock rise time 1 1 m s t chcl 2 t fc clock fall time 1 1 m s t dvch t dsu data in setup time 40 20 ns t chdx t dh data in hold time 50 30 ns t hhch clock low hold time after hold not active 140 70 ns t hlch clock low hold time after hold active 90 40 ns t clhl clock high set-up time before hold active 0 0 ns t clhh clock high set-up time before hold not active 0 0 ns t shqz 2 t dis output disable time 250 100 ns t clqv t v clock low to output valid 150 60 ns t clqx t ho output hold time 0 0 ns t qlqh 2 t ro output rise time 100 50 ns t qhql 2 t fo output fall time 100 50 ns t hhqx 2 t lz hold high to output low-z 100 50 ns t hlqz 2 t hz hold low to output high-z 250 100 ns t w t wc write time 10 5 ms
23/34 m95160, m95080 table 20. ac characteristics (m95xxx-w, temperature range 6) note: 1. t ch +t cl 1/f c . 2. value guaranteed by characterization, not 100% tested in production. 3. to be characterized. 4. preliminary: this product is under development. for more information, please contact your nearest st sales office. test conditions specified in table 11 and table 9 symbol alt. parameter min. max. min. 4 max. 4 unit f c f sck clock frequency d.c. 2 d.c. 5 mhz t slch t css1 s active setup time 200 90 ns t shch t css2 s not active setup time 200 90 ns t shsl t cs s deselect time 200 100 ns t chsh t csh s active hold time 200 90 ns t chsl s not active hold time 200 90 ns t ch 1 t clh clock high time 200 90 ns t cl 1 t cll clock low time 200 90 ns t clch 2 t rc clock rise time 1 1 m s t chcl 2 t fc clock fall time 1 1 m s t dvch t dsu data in setup time 40 20 ns t chdx t dh data in hold time 50 30 ns t hhch clock low hold time after hold not active 140 70 ns t hlch clock low hold time after hold active 90 40 ns t clhl clock high set-up time before hold active 0 0 ns t clhh clock high set-up time before hold not active 0 0 ns t shqz 2 t dis output disable time 250 100 ns t clqv t v clock low to output valid 150 60 ns t clqx t ho output hold time 0 0 ns t qlqh 2 t ro output rise time 100 50 ns t qhql 2 t fo output fall time 100 50 ns t hhqx 2 t lz hold high to output low-z 100 50 ns t hlqz 2 t hz hold low to output high-z 250 100 ns t w t wc write time 10 5 ms
m95160, m95080 24/34 table 21. ac characteristics (m95xxx-w, temperature range 3) note: 1. t ch +t cl 1/f c . 2. value guaranteed by characterization, not 100% tested in production. 3. to be characterized. 4. preliminary: this product is under development. for more information, please contact your nearest st sales office. test conditions specified in table 11 and table 9 symbol alt. parameter min. max. min. 4 max. 4 unit f c f sck clock frequency d.c. 2 d.c. 5 mhz t slch t css1 s active setup time 200 90 ns t shch t css2 s not active setup time 200 90 ns t shsl t cs s deselect time 200 100 ns t chsh t csh s active hold time 200 90 ns t chsl s not active hold time 200 90 ns t ch 1 t clh clock high time 200 90 ns t cl 1 t cll clock low time 200 90 ns t clch 2 t rc clock rise time 1 1 m s t chcl 2 t fc clock fall time 1 1 m s t dvch t dsu data in setup time 40 20 ns t chdx t dh data in hold time 50 30 ns t hhch clock low hold time after hold not active 140 70 ns t hlch clock low hold time after hold active 90 40 ns t clhl clock high set-up time before hold active 0 0 ns t clhh clock high set-up time before hold not active 0 0 ns t shqz 2 t dis output disable time 250 100 ns t clqv t v clock low to output valid 150 60 ns t clqx t ho output hold time 0 0 ns t qlqh 2 t ro output rise time 100 50 ns t qhql 2 t fo output fall time 100 50 ns t hhqx 2 t lz hold high to output low-z 100 50 ns t hlqz 2 t hz hold low to output high-z 250 100 ns t w t wc write time 10 5 ms
25/34 m95160, m95080 table 22. ac characteristics (m95xxx-s) note: 1. t ch +t cl 1/f c . 2. value guaranteed by characterization, not 100% tested in production. 3. to be characterized. 4. preliminary: this product is under development. for more information, please contact your nearest st sales office. test conditions specified in table 11 and table 10 symbol alt. parameter min. 4 max. 4 unit f c f sck clock frequency d.c. 2 mhz t slch t css1 s active setup time 80 ns t shch t css2 s not active setup time 80 ns t shsl t cs s deselect time 200 ns t chsh t csh s active hold time 100 ns t chsl s not active hold time 100 ns t ch 1 t clh clock high time 200 ns t cl 1 t cll clock low time 200 ns t clch 2 t rc clock rise time 1 m s t chcl 2 t fc clock fall time 1 m s t dvch t dsu data in setup time 50 ns t chdx t dh data in hold time 50 ns t hhch clock low hold time after hold not active 80 ns t hlch clock low hold time after hold active 80 ns t clhl clock high set-up time before hold active 0 ns t clhh clock high set-up time before hold not active 0 ns t shqz 2 t dis output disable time 100 ns t clqv t v clock low to output valid 100 ns t clqx t ho output hold time 0 ns t qlqh 2 t ro output rise time 90 ns t qhql 2 t fo output fall time 90 ns t hhqx 2 t lz hold high to output low-z 100 ns t hlqz 2 t hz hold low to output high-z 100 ns t w t wc write time 5 ms
m95160, m95080 26/34 figure 17. serial input timing figure 18. hold timing c d ai01447c s msb in q tdvch high impedance lsb in tslch tchdx tchcl tclch tshch tshsl tchsh tchsl c q ai01448 s d hold tclhl thlch thhch tclhh thhqx thlqz
27/34 m95160, m95080 figure 19. output timing c q ai01449d s lsb out d addr.lsb in tshqz tch tcl tqlqh tqhql tclqx tclqv tclqx tclqv
m95160, m95080 28/34 package mechanical pdip8 8 pin plastic dip, 0.25mm lead frame note: 1. drawing is not to scale. pdip8 8 pin plastic dip, 0.25mm lead frame pdip-b a2 a1 a l be d e1 8 1 c ea b2 eb e symb. mm inches typ. min. max. typ. min. max. a 5.33 0.210 a1 0.38 0.015 a2 3.30 2.92 4.95 0.130 0.115 0.195 b 0.46 0.36 0.56 0.018 0.014 0.022 b2 1.52 1.14 1.78 0.060 0.045 0.070 c 0.25 0.20 0.36 0.010 0.008 0.014 d 9.27 9.02 10.16 0.365 0.355 0.400 e 7.87 7.62 8.26 0.310 0.300 0.325 e1 6.35 6.10 7.11 0.250 0.240 0.280 e 2.54 0.100 ea 7.62 0.300 eb 10.92 0.430 l 3.30 2.92 3.81 0.130 0.115 0.150
29/34 m95160, m95080 so8 narrow 8 lead plastic small outline, 150 mils body width note: drawing is not to scale. so8 narrow 8 lead plastic small outline, 150 mils body width so-a e n cp b e a d c l a1 a 1 h hx45 symb. mm inches typ. min. max. typ. min. max. a 1.35 1.75 0.053 0.069 a1 0.10 0.25 0.004 0.010 b 0.33 0.51 0.013 0.020 c 0.19 0.25 0.007 0.010 d 4.80 5.00 0.189 0.197 e 3.80 4.00 0.150 0.157 e 1.27 0.050 h 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 l 0.40 0.90 0.016 0.035 a 0 8 0 8 n8 8 cp 0.10 0.004
m95160, m95080 30/34 tssop8 8 lead thin shrink small outline note: 1. drawing is not to scale. tssop8 8 lead thin shrink small outline tssop8-m 1 8 cp c l e e1 d a2 a a e b 4 5 a1 l1 symbol mm inches typ. min. max. typ. min. max. a 1.200 0.0472 a1 0.050 0.150 0.0020 0.0059 a2 1.000 0.800 1.050 0.0394 0.0315 0.0413 b 0.190 0.300 0.0075 0.0118 c 0.090 0.200 0.0035 0.0079 cp 0.100 0.0039 d 3.000 2.900 3.100 0.1181 0.1142 0.1220 e 0.650 0.0256 e 6.400 6.200 6.600 0.2520 0.2441 0.2598 e1 4.400 4.300 4.500 0.1732 0.1693 0.1772 l 0.600 0.450 0.750 0.0236 0.0177 0.0295 l1 1.000 0.0394 a 0 8 0 8
31/34 m95160, m95080 tssop14 - 14 lead thin shrink small outline note: 1. drawing is not to scale. tssop14 - 14 lead thin shrink small outline tssop14-m 1 14 cp c l e e1 d a2 a a e b 7 8 a1 l1 symbol mm inches typ. min. max. typ. min. max. a 1.200 0.0472 a1 0.050 0.150 0.0020 0.0059 a2 1.000 0.800 1.050 0.0394 0.0315 0.0413 b 0.190 0.300 0.0075 0.0118 c 0.090 0.200 0.0035 0.0079 cp 0.100 0.0039 d 5.000 4.900 5.100 0.1969 0.1929 0.2008 e 0.650 0.0256 e 6.400 6.200 6.600 0.2520 0.2441 0.2598 e1 4.400 4.300 4.500 0.1732 0.1693 0.1772 l 0.600 0.500 0.750 0.0236 0.0197 0.0295 l1 1.000 0.0394 a 0 8 0 8
m95160, m95080 32/34 part numbering table 23. ordering information scheme note: 1. tssop14, 169 mil width, package is available for the m95160 series only. 2. tssop8, 169 mil width, package is available for the m95080 series only. for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales of- fice. example: m95160 w mn 6 t device type m95 = spi serial access eeprom device function 160 = 16 kbit (2048 x 8) 080 = 8 kbit (1024 x 8) operating voltage blank = v cc = 4.5 to 5.5v w=v cc = 2.5 to 5.5v s=v cc = 1.8 to 3.6v package bn = pdip8 (0.25 mm frame) mn = so8 (150 mil width) dl 1 = tssop14 (169 mil width) dw 2 = tssop8 (169 mil width) temperature range 6=40to85 c 3 = 40 to 125 c optio n t = tape & reel packing
33/34 m95160, m95080 revision history table 24. document revision history date rev. description of revision 19-jul-2001 1.0 document written from previous m95640/320/160/080 data sheet 06-feb-2002 1.1 announcement made of planned upgrade to 10 mhz clock for the 5v, 40 to 85 c, range.
m95160, m95080 34/34 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in lif e support devices or systems without express written approval of stmicroelectronics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners ? 2002 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states. www.st.com

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